1. Field of the Invention
The invention relates to a display panel and in particular to a display panel with corrosion protection.
2. Description of the Related Art
Flat panel display devices commonly use LCD panels. An LCD panel may include a pixel region having an array of pixel thin film transistors and intersecting arrays of spaced data lines and gate lines connected to the array of pixel thin film transistors. The array of pixel thin film transistors, data lines and gate lines form an array of addressable pixels. The LCD panel may also include a peripheral region associated with driver integrated circuit chips (ICs), which drive the array of pixel thin film transistors. The ICs may be mounted to the LCD panel in the peripheral region thereof using a chip-on-glass (COG), tape-carrier-package (TCP) or chip-on-film (COF) technology. In COG, TCP and COF, anisotropic conductive films (ACFs) bond the driver ICs or the flexible printed circuits or other films which carry driver ICs to the LCD panel.
FIG. 1 is a plane view of a traditional LCD panel 100. The panel 100 includes a pixel region 101 and a peripheral region 103, which comprises a chip bonding region 105 with a plurality of chip bonding pads (not shown), and fringe circuit 107 with a plurality of test pads (not shown). The pixel region 101 has a pixel thin film transistor (TFT) array with conductive gate and data lines (not shown).
The fringe circuit region 107 serves as a signal receiver during array testing, or is connected to an ESD (electrostatics discharge) circuit, providing electrostatic protection. The fringe circuit is provided adjacent to a chip bonding region 105 of the LCD panel. The fringe circuit is electrically connected to a group of terminal pads disposed on the surface of the LCD panel, which are electrically connected to the integrated circuits (ICs) with anisotropic conductive film bonds.
FIG. 2A is a cross-section diagram of the peripheral region 103 of the traditional LCD panel 100 along the dash line A-A′. As shown in FIG. 2A, the peripheral region 103 comprises a substrate 201 having a chip bonding region 105 and a fringe circuit region 107, and a conductive layer 203 disposed thereon. The chip bonding region 105 is separated apart from the fringe circuit region 107 by an insulating layer 207. A conductive layer 205 is formed covering the conductive layer 203 and part of the top surfaces of the insulating layer 207, exposing a cut region 209 of the insulating layer 207. The fringe circuit region is used to receive the driving signals during the array test or protect the electrostatics discharge damage during the manufacturing process. After a cell process, the fringe circuit region 107 is removed by cutting through the cut region 209 within the insulating layer 207, exposing the sidewall of the conductive layer 203 to the air, as shown in FIG. 2B, such that the exposed sidewall 210 of the conductive layer 203 is corroded. The corrosion extends to the bonding pads through the conductive layer resulting in failure of signal transmission